Start Updating storm os

Updating storm os

Ice Pack/Ice Unpack, Ice Box, Ice Prog, Ice Time, and Ice PLL are written by Clifford Wolf.

Please file an issue on github if you have additional notes to share regarding the install procedures on the operating system of your choice.

The Ice Storm Tools are a couple of small programs for working with i CE40 bitstream files and our ASCII representation of it.

The Ice Storm Makefile builds and installs two files: .

This files contain all the relevant information for arachne-pnr to place&route a design and create an Ice Storm ASCII file for the placed and routed design.

If your question is a general question about Verilog HDL design, please consider using the verilog tag on stackoverflow instead.

For general discussions go to the Yosys Subreddit or #yosys on freenode IRC.

For example, consider the following Verilog and PCF files: $ icebox_explain Reading file 'example.asc'..

Fabric size (without IO tiles): 12 x 16 .io_tile 0 10 IOB_1 PINTYPE_0 IOB_1 PINTYPE_3 IOB_1 PINTYPE_4 Io Ctrl IE_0 Io Ctrl IE_1 Io Ctrl REN_0 buffer local_g0_5 io_1/D_OUT_0 buffer logic_op_tnr_5 local_g0_5 .io_tile 0 14 IOB_1 PINTYPE_0 Io Ctrl IE_1 Io Ctrl REN_0 buffer io_1/D_IN_0 span4_vert_b_6 .io_tile 0 11 IOB_0 PINTYPE_0 Io Ctrl IE_0 Io Ctrl REN_1 routing span4_vert_t_14 span4_horz_13 .logic_tile 1 11 LC_5 0001000000000000 0000 buffer local_g0_0 lutff_5/in_1 buffer local_g3_0 lutff_5/in_0 buffer neigh_op_lft_0 local_g0_0 buffer sp4_h_r_24 local_g3_0$ icebox_vlog -p // Reading file 'example.asc'..

2016-01-17: First release of Ice Time timing analysis. 2015-05-27: We have a working fully Open Source flow with Yosys and Arachne-pnr!

Video: https://youtu.be/IG5Cp FJRn Ok 2015-12-27: Presentation of the Ice Storm flow at 32C3 (Video on Youtube). Video: Ui Nlmv VOq8 2015-04-13: Complete rewrite of Ice Unpack, added Ice Pack, some major documentation updates 2015-03-22: First public release and short You Tube video demonstrating our work: SNDQMM Project Ice Storm aims at reverse engineering and documenting the bitstream format of Lattice i CE40 FPGAs and providing simple tools for analyzing and creating bitstream files.

If you have a bug report please file an issue on github.